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VP of Silicon

Company: Lever
Location: Union City
Posted on: April 4, 2021

Job Description:

Fathom Radiant is building computer hardware to train neural networks at the human brain-scale and beyond. By combining the complementary strengths of optics and electronics, we have developed a revolutionary interconnect fabric that enables a flexible machine with the network capacity of a supercomputer and unprecedented scalability. Help us construct the future of machine intelligence. Our founding team has previously founded startups with more than $500 million in exits. We are well-funded from investors including Khosla Ventures, Jeff Bezos, and many others. We're seeking a VP of Silicon to lead silicon development at Fathom Radiant. The ideal candidate will have experience leading advanced node tape-outs of novel architectures as well as a track record of strong individual contribution. In this role, you will help define the future of computer architecture, with the incredible bandwidth and scalability of Fathom's hardware opening up new architectural possibilities that are impossible with existing computer hardware. You will collaborate closely with Fathom Radiant's software teams, as well as colleagues from disciplines such as optics and optoelectronics, to develop the silicon that enables novel optoelectronic hardware. Areas of contribution

  • Lead the design and implementation of all aspects of Fathom Radiant's custom silicon, from microarchitecture design and RTL to testing and packaging
  • Closely collaborate with the software team to define Fathom Radiant's custom ISA, architecture, and microarchitecture, with a software- and user-centric mindset
  • Collaborate with other engineering teams to enable the integration of Fathom Radiant's silicon into the system and to enable Fathom Radiant's proprietary optical interconnect
  • Oversee the digital silicon architecture, IC design/implementation/validation, and collaboration with software teams to build accurate simulation tools
  • Help drive the cross disciplinary optimization considering aspects from ML algorithms to physical implementation
  • Analyze the performance of state of the art deep learning models on fathom hardware Requirements
    • Experience leading new architectures from design to successful tape-outs in advanced nodes
    • Significant academic or industry experience in computer architecture and SoC design with expert level understanding of the underlying electronics
    • Experience with deep learning algorithms and ML accelerators
    • Expertise in all aspects of chip design across architecture, logic and physical design, fabrication, and testing of VLSI ICs
    • Experience in system-level design, high speed memory and communication interfaces (e.g. HBM, PCIe, etc.)
    • Proficiency in HDL languages, such as Verilog/Systemverilog or VHDL
    • Excellent communication skills and ability to collaborate on complex cross-disciplinary systems
    • Drive to build something that hasn't been built before Preferred
      • Experience in parallel program compilation and optimization
      • Experience in atypical architectures is welcome You'll do well here if...
        • You enjoy thoughtful discussions fueled by problem-solving and logic
        • You're comfortable both leading and contributing individually
        • You're excited about the future of ML hardware
        • You enjoy teaching and learning from an interdisciplinary team We highly encourage submission of a cover letter, just tell us why you're here :)

Keywords: Lever, Union City , VP of Silicon, Executive , Union City, California

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